Memory devices are often shared by multiple electronic devices in a computer system to reduce the number and overall costs of system components, as well as facilitate communication between the resource sharing electronic devices. Arbiter circuits are generally included in such systems to prevent collisions between multiple electronic devices simultaneously attempting to access the memory device. If the memory device is a single-port memory device, only one resource sharing device can access the memory device at a time. Therefore, arbiter circuits in systems employing such single-port memory devices, arbitrate contention by allowing only a contention winning electronic device temporary, sole access to the entire memory device. For a dual-port memory device, on the other hand, two electronic devices can concurrently read access the same location and write access different locations of the memory device, thus providing nearly twice the bandwidth of a single-port device. Access is only restricted when the electronic devices simultaneously attempt to write access the same location. Therefore, arbiter circuits in systems employing such dual-port memory devices, arbitrate contention by allowing only a contention winning electronic device temporary sole write access to the simultaneously requested location.
FIG. 1 illustrates, as an example, a block diagram of a computer system 100 including a conventional dual-port static random-access memory (SRAM) 101 with selected characteristics simplistically depicted in bubble blow-ups, 110 and 112, for descriptive purposes, and left and right electronic devices, 105 and 106, respectively coupled to the dual-port SRAM 101 by left and right ports, 103 and 104. As simplistically depicted in bubble blow-up 110, one characteristic and significant drawback of the conventional dual-port SRAM 101 is the large size of its individual memory cells (e.g., 114), which may be as large as eight or six transistors, for example, to accommodate its dual porting to both left and right ports, 103 and 104, through lines 121 and 122. Also, as simplistically depicted in bubble blow-up 112, another characteristic and significant drawback of the conventional dual-port SRAM 101 is that its arbiter logic arbitrates at the individual memory cell level, which can add to access times.
It is a goal of integrated circuit design to minimize the die size and consequently, the cost of an integrated circuit device. Another goal is to maximize the performance of the integrated circuit device. Both of these goals are ongoing and especially important in designing high density memory devices for advanced computer systems.